Browsing by Author "Bati, B"

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The Bias-Dependence Change of Barrier Height of Schottky Diodes Under Forward Bias by Including the Series Resistance Effect
(Royal Swedish Acad Sciences, 1996) Turut, A; Bati, B; Kokce, A; Saglam, M; Yalcin, N
Schottky barrier height shifts depending on the interfacial layer as well as a change of the interface state charge with the forward bias while considering the presence of bulk (semiconductor) series resistance are discussed both theoretically and experimentally. It has been concluded that the barrier height shift or increase in Schottky diodes is mainly due to the potential change across the interfacial layer and the occupation of the interface states as a result of the applied forward voltage. One assumes that the barrier height is controlled by the density distribution of the interface states in equilibrium with the semiconductor and the applied voltage. In nonideal Schottky diodes, the values of the voltage drops across the interfacial layer, the depletion layer and the bulk resistance are given in terms of the bias dependent ideality factor, n, different from those in literature. These values are determined by a formula obtained for V-i and V-s by means of change of the interface charge with bias.
Dependence of Thermal Annealing on the Density Distribution of Interface States in Ti/N-gaas(te) Schottky Diodes
(Elsevier Science Bv, 1999) Ayyildiz, E; Bati, B; Temirci, C; Türüt, A
The Ti/n-GaAs(Te) Schottky barrier diodes have been annealed in the temperature range 200-400 degrees C with steps of 100 degrees C for 5 min. The barrier height value has increased with increasing annealing temperature. This increase has been attributed to that the annealing removes the passivation effect of the native oxide layer and reactivates the surface defects which are responsible for the Fermi level pinning. The value of equilibrium interface charge density Q(ss)(0) has increased with increasing annealing temperature. It has been found that the experimental density distribution curves of the interface states and the values of equilibrium interface charge density Q(ss)(0) has confirmed this interpretation. The results indicate that the negative equilibrium interface charge is responsible for the actual equilibrium barrier height value. (C) 1999 Elsevier Science B.V. All rights reserved.
The Effect of Series Resistance on Calculation of the Interface State Density Distribution in Schottky Diodes
(Taylor & Francis Ltd, 2001) Ayyildiz, E; Temirci, C; Bati, B; Türüt, A
This work presents an attempt related to the importance of the fact that the series resistance value is considered in calculating the interface state density distribution from the non-ideal forward bias current-voltage (I-V) characteristics of Au/n-Si Schottky barrier diodes (SBDs). To examine the consistency of this approach, Au/n-Si SBDs with Si bulk thicknesses of 200 and 400 mum have been prepared. Both diodes showed non-ideal I-V behaviour with ideality factors of 1.14 and 1.12, respectively, and thus it has been thought that the diodes have a metal-interface layer-semiconductor configuration. At the same energy position near the bottom of the conduction band, the interface state density (N-SS) values, without taking into account the series resistance value of the devices, are almost one order of magnitude larger than the N-SS values obtained taking into account the series resistance value.
Effect of Thermal Annealing on Co/N-lec Gaas (Te) Schottky Contacts
(Pergamon-elsevier Science Ltd, 2000) Nuhoglu, Ç; Temirci, C; Bati, B; Biber, M; Türüt, A
The Co/n-GaAs(Te) Schottky barrier diodes have been annealed at temperatures from 100 to 300 degrees C for 5 min and from 350 to 800 degrees C for 1 min in N-2 atmosphere. Some expressions have been obtained to interpret the relation between the experiment barrier height Phi(b,o) and equilibrium interface charge density Q(ss)(0) depending on annealing temperature. The Phi(b,o) value has increased and Q(ss)(0) is decreased with increasing annealing temperature up to 550 degrees C. This increase in the barrier height has been attributed to the value of positive Q(ss)(0), which is responsible for the Fermi level pinning. The relation between the Phi(b,o), and Q(ss)(0) depending on annealing temperature is in very good agreement with that of the interface state density distribution especially in the mid-gap. (C) 2000 Elsevier Science Ltd. All rights reserved.
High-Barrier Height Sn/P-si Schottky Diodes With Interfacial Layer by Anodization Process
(Elsevier Science Bv, 2001) Temircl, C; Bati, B; Saglam, M; Türüt, A
We have fabricated the Sn/p-Si Schottky barrier diodes with different surface treatments. Prior to the Sn evaporation on the p-Si(0 0 1), the first kinds of samples consisted of a dip in diluted aqueous HF solution followed by a rinse in de-ionized water (sample 1, SDI), the second kinds of samples several steps of anodization in aqueous KOH solution each followed by a dip in diluted aqueous HF solution and a subsequent rinse in de-ionized water (sample 2, SD2), and the third kinds of samples one anodization step only (sample 3, SD3). We have found the lowest values of both the barrier heights and ideality factors with the diodes of preparation type SD2. The anodization, on the other hand, have increased both, the barrier heights as well as the ideality factors. The extrapolation of the barrier heights versus ideality factors plot to the ideality factor determined by the image force effect have given the laterally homogeneous barrier heights of approximately 0.75 and 0.92 eV for the SD2 and SD3 diodes. Furthermore, we have calculated a mean tunneling barrier height of (chi) = 0.12 eV for the MIS Sn/p-Si diodes with the anodic oxide layer. (C) 2001 Elsevier Science B.V. All rights reserved.
On the Forward Bias Excess Capacitance at Intimate and Mis Schottky Barrier Diodes With Perfect or Imperfect Ohmic Back Contact
(Royal Swedish Acad Sciences, 2000) Bati, B; Nuhoglu, Ç; Saglam, M; Ayyildiz, E; Turüt, A
An experimental explanation of the forward bias Capacitance;frequency plots for intimate or MIS SBDs with perfect or imperfect ohmic back-contact has been made. It has been shown that there is no excess capacitance that could be ascribed to the interface states or minority carrier at the intimate SBDs (that is, without interfacial layer) with the perfect ohmic back contact (low-resistance). It has been found that the excess capacitance is only measurable at SBDs with imperfect back contacts or with an interfacial layer which separates the interface states from the metal. It has been found that excess capacitance can be generated by varying the resistance or quality of the back-ohmic contact to the bulk semiconductor substrate, that is, the density of minority carriers that are injected by the Schottky contact depends sensitively on the properties of the ohmic back-contact. Again, it has been seen that the excess capacitance has appeared owing to the interface states plus minority carriers in MIS SBDs with imperfect back contacts. Thus, it has been concluded that the excess capacitance at nonideal Schottky contacts has been caused not only by the interface states but also by the minority carriers or by the interface states plus minority carriers due to the poor frontside or poor backside contacts. Thereby it has been experimentally shown that every forward bias C-f-plots with excess capacitance cannot be used to extract the results related to the interface states.