Browsing by Author "Ayyildiz, E"

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Dependence of Thermal Annealing on the Density Distribution of Interface States in Ti/N-gaas(te) Schottky Diodes
(Elsevier Science Bv, 1999) Ayyildiz, E; Bati, B; Temirci, C; Türüt, A
The Ti/n-GaAs(Te) Schottky barrier diodes have been annealed in the temperature range 200-400 degrees C with steps of 100 degrees C for 5 min. The barrier height value has increased with increasing annealing temperature. This increase has been attributed to that the annealing removes the passivation effect of the native oxide layer and reactivates the surface defects which are responsible for the Fermi level pinning. The value of equilibrium interface charge density Q(ss)(0) has increased with increasing annealing temperature. It has been found that the experimental density distribution curves of the interface states and the values of equilibrium interface charge density Q(ss)(0) has confirmed this interpretation. The results indicate that the negative equilibrium interface charge is responsible for the actual equilibrium barrier height value. (C) 1999 Elsevier Science B.V. All rights reserved.
The Effect of Series Resistance on Calculation of the Interface State Density Distribution in Schottky Diodes
(Taylor & Francis Ltd, 2001) Ayyildiz, E; Temirci, C; Bati, B; Türüt, A
This work presents an attempt related to the importance of the fact that the series resistance value is considered in calculating the interface state density distribution from the non-ideal forward bias current-voltage (I-V) characteristics of Au/n-Si Schottky barrier diodes (SBDs). To examine the consistency of this approach, Au/n-Si SBDs with Si bulk thicknesses of 200 and 400 mum have been prepared. Both diodes showed non-ideal I-V behaviour with ideality factors of 1.14 and 1.12, respectively, and thus it has been thought that the diodes have a metal-interface layer-semiconductor configuration. At the same energy position near the bottom of the conduction band, the interface state density (N-SS) values, without taking into account the series resistance value of the devices, are almost one order of magnitude larger than the N-SS values obtained taking into account the series resistance value.
On the Forward Bias Excess Capacitance at Intimate and Mis Schottky Barrier Diodes With Perfect or Imperfect Ohmic Back Contact
(Royal Swedish Acad Sciences, 2000) Bati, B; Nuhoglu, Ç; Saglam, M; Ayyildiz, E; Turüt, A
An experimental explanation of the forward bias Capacitance;frequency plots for intimate or MIS SBDs with perfect or imperfect ohmic back-contact has been made. It has been shown that there is no excess capacitance that could be ascribed to the interface states or minority carrier at the intimate SBDs (that is, without interfacial layer) with the perfect ohmic back contact (low-resistance). It has been found that the excess capacitance is only measurable at SBDs with imperfect back contacts or with an interfacial layer which separates the interface states from the metal. It has been found that excess capacitance can be generated by varying the resistance or quality of the back-ohmic contact to the bulk semiconductor substrate, that is, the density of minority carriers that are injected by the Schottky contact depends sensitively on the properties of the ohmic back-contact. Again, it has been seen that the excess capacitance has appeared owing to the interface states plus minority carriers in MIS SBDs with imperfect back contacts. Thus, it has been concluded that the excess capacitance at nonideal Schottky contacts has been caused not only by the interface states but also by the minority carriers or by the interface states plus minority carriers due to the poor frontside or poor backside contacts. Thereby it has been experimentally shown that every forward bias C-f-plots with excess capacitance cannot be used to extract the results related to the interface states.