Browsing by Author "Meral, M. E."

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Experimental and Simulation Based Study of an Adaptive Filter Controlled Solid State Transfer Switch
(Springer, 2014) Meral, M. E.; Cuma, M. U.; Teke, A.; Tumay, M.; Bayindir, K. C.
The most common power quality problems in electrical distribution systems are related to single phase to ground faults causing unbalanced voltage sags. One of the most widely used methods for sag detection is conventional method based on d-q transformation. However, this method has the disadvantage of missing the detection of single phase-to-ground faults, because this method uses a voltage sag level signal obtained from the average of three phase voltages for sag detection. In this paper, an adaptive filter based sag detection method is proposed for solid state transfer switch (SSTS). Simulation models of the SSTS using the adaptive filter based proposed and d-q transformation based methods are developed by PSCAD/EMTDC program. Simulation results show that, the SSTS using proposed method is able to detect three phases and/or single phase voltage sags, correctly. To validate the simulation model and results, a three-phase experimental SSTS prototype is successfully constructed and experimental results are presented.
Using Active Power Factor Correction (Pfc) Boost Rectifiers for an Improved Topology of Static Series Compensators With No Energy Storage
(inst Engineering Technology-iet, 2012) Meral, M. E.
Static series compensator (SSC) topologies including shunt connected power electronic rectifier with no energy storage have some potential advantages such as an extra saving and the ability exists to compensate longer dips. However, this topology has the disadvantage that the uncontrolled DC link is connected to the supply with a shunt rectifier during the fault, and more importantly, the conventional diode bridge rectifier (C-DBR) does not draw sinusoidal current from the supply and inject current harmonics to the network. In this study, an improved topology for the SSCs using a single-switch active power factor correction (A-PFC) boost rectifier is proposed. Single-phase SSC topologies with load side shunt connected C-DBR and A-PFC are compared by obtaining the results for the DC-link voltages, the supply currents and the load voltages. The results show that the proposed new topology offers solutions to problems of the topology including C-DBR such as supply current harmonics and uncontrolled DC-link voltage and so a considerable performance improvement is achieved by using the proposed SSC topology.
Improved Phase-Locked Loop for Robust and Fast Tracking of Three Phases Under Unbalanced Electric Grid Conditions
(inst Engineering Technology-iet, 2012) Meral, M. E.
Modern electric power transmission and distribution systems need accurate phase information on three-phase grid voltages and/or currents. Conventional three-phase synchronous reference frame-based phase-locked loop (SRF-PLL) is generally sufficient for phase tracking during balanced operating conditions. However, SRF-PLL becomes inadequate when unbalance exists in the three-phase input signal. Because, unbalance in input signal set causes a double-frequency ripple and as a result, an ideal output signal cannot be obtained. Previous studies have focused on improving the SRF-PLL performance by removing this ripple with using delayed signals methods such as delayed signal cancellation (DSC)-PLL methods. Although these methods give ideal output signals, a certain time delay is occurred. In this study, an effective method DIF-PLL based on adding another signal, which has reverse polarity ripple is proposed for obtaining ideal output signal and fast tracking of phase angle. Performance of the DIF-PLL is compared with the performances of SRF-PLL and DSC-PLL methods. The performances of these methods are also examined for the presence of the harmonics. The results show that the proposed method has a better three-phase tracking performance than the others under balanced and unbalanced electric grid conditions.