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Design of a 21-Level Multilevel Inverter With Minimum Number of Devices Count

dc.authorid Karakilic, Murat/0000-0001-5323-2583
dc.authorscopusid 58484895900
dc.authorscopusid 57212267650
dc.authorscopusid 36185082500
dc.authorwosid Hatas, Hasan/Hhz-2397-2022
dc.contributor.author Karakilic, Murat
dc.contributor.author Hatas, Hasan
dc.contributor.author Almali, M. Nuri
dc.date.accessioned 2025-05-10T17:21:33Z
dc.date.available 2025-05-10T17:21:33Z
dc.date.issued 2023
dc.department T.C. Van Yüzüncü Yıl Üniversitesi en_US
dc.department-temp [Karakilic, Murat] Igdir Univ, Dept Elect & Elect, Igdir, Turkiye; [Hatas, Hasan; Almali, M. Nuri] Van Yuzuncu Yil Univ, Elect Engn Dept, Van, Turkiye en_US
dc.description Karakilic, Murat/0000-0001-5323-2583 en_US
dc.description.abstract Multilevel inverters (MLIs) have attracted the attention of researchers for their needs in industrial applications, renewable energy systems, and electric vehicles. MLIs require a large number of power electronic components to synthesize higher levels at the output voltage. However, overuse of power electronic devices increases the complexity, losses, and cost of MLIs. In this study, a new MLI has been proposed with a reduced number of power switches. The basic unit of the proposed MLI comprises only three independent DC sources and 10 switches (eight unidirectional and two bidirectional) to produce 21 levels at the output voltage waveform. The nearest level control (NLC) modulation method has been used to produce gate pulses. Furthermore, three extension topologies have been proposed to generate a higher number of levels, and the extension parameters have been compared with recently introduced and conventional topologies. The comparative study shows that the proposed MLI topology requires fewer components in terms of power electronics parameters than the others. On the other hand, the presented first extension study that can be used for all non-extendable basic units is one of the prominent values of the study. Simulation studies showing modulation methods, switching patterns, and signal outputs were performed with Matlab/Simulink. A prototype of the proposed main module has been realized and tested in the laboratory with an FPGA processing board. Experimental results have been verified with simulation results, and the performance of the proposed topology has been proven. en_US
dc.description.woscitationindex Science Citation Index Expanded
dc.identifier.doi 10.1002/cta.3730
dc.identifier.endpage 5723 en_US
dc.identifier.issn 0098-9886
dc.identifier.issn 1097-007X
dc.identifier.issue 12 en_US
dc.identifier.scopus 2-s2.0-85164561188
dc.identifier.scopusquality Q3
dc.identifier.startpage 5705 en_US
dc.identifier.uri https://doi.org/10.1002/cta.3730
dc.identifier.uri https://hdl.handle.net/20.500.14720/10430
dc.identifier.volume 51 en_US
dc.identifier.wos WOS:001024032800001
dc.identifier.wosquality Q3
dc.language.iso en en_US
dc.publisher Wiley en_US
dc.relation.publicationcategory Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı en_US
dc.rights info:eu-repo/semantics/openAccess en_US
dc.subject Fpga Implementation en_US
dc.subject Multilevel Inverter en_US
dc.subject Nearest Level Control en_US
dc.subject Reduced Switch Count en_US
dc.title Design of a 21-Level Multilevel Inverter With Minimum Number of Devices Count en_US
dc.type Article en_US

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